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64-bit PCI-X Host Bridge
The EP423 64-bit PCI-X host bridge core is optimized to operate in both PCI mode and PCI-X mode. The user interface is a highly efficient and flexible user interface which provides for easy integration with other user logic. This PCI-X core automatically switch between PCI and PCI-X protocol based on the system environment. It supports both PCI version 2.3 and PCI-X version 1.0b.
The EP423 64-bit PCI-X host bridge core is designed so that user interface can operate at any clock speed independent of the PCI bus speed. The user interface clock and PCI bus clock can be synchronous our asynchronous to each other. The core utilizes double write buffer for write posting in both the master and target direction. The double data buffer design approach allows data access by the user interface and the PCI interface simultaneously and independent from each othe
When function as a master, the controller is capable of initiating memory or IO read and write upon user requests. The type of command and the burst size are specified by the user for each data transaction. Burst size can be determined by the user on a per transaction basis.
Once a master transfer begins, the core monitors the target device's signals on the PCI and PCI-X bus and transfer data to the user logic. All different types of transfer terminations such as retry, disconnect and split response are handled by the core. If a transfer is retry or disconnected by the target, the master core restarts the transfer automatically without the assistance of the user logic. Bus request, bus parking, parity detection and generation all are handled by the core. If a transaction is terminated with split response, the master would wait for the split completion transfer from the target.
The target controller is capable of handling memory and IO accesses on the PCI and PCI-X bus. All memory/IO accesses are supported. Configuration register read and write transactions are supported locally by the bus target without assistance from the user logic. Memory and I/O write to the target are posted in the write buffer before they are transferred to the user. Memory and I/O read are handled as delay read on PCI bus and as split transaction on PCI-X bus. The user interface allows the user to control the characteristics of the access. For example, the user can insert a wait state or transfer data without wait state according to its data bandwidth.
As a host bridge, this PCI-X IP is also capable of initiating PCI and PCI-X configuration access on the bus. This feature allows the host CPU to initiate the bus system during system power up. The PCI-X core contains the CONFIG_ADDR and CONFIG_DATA registers and address decoding circuitry so that the standard PCI configuration mechanism can be used.
The EP423 64-bit PCI-X host bridge core is designed so that user interface can operate at any clock speed independent of the PCI bus speed. The user interface clock and PCI bus clock can be synchronous our asynchronous to each other. The core utilizes double write buffer for write posting in both the master and target direction. The double data buffer design approach allows data access by the user interface and the PCI interface simultaneously and independent from each othe
When function as a master, the controller is capable of initiating memory or IO read and write upon user requests. The type of command and the burst size are specified by the user for each data transaction. Burst size can be determined by the user on a per transaction basis.
Once a master transfer begins, the core monitors the target device's signals on the PCI and PCI-X bus and transfer data to the user logic. All different types of transfer terminations such as retry, disconnect and split response are handled by the core. If a transfer is retry or disconnected by the target, the master core restarts the transfer automatically without the assistance of the user logic. Bus request, bus parking, parity detection and generation all are handled by the core. If a transaction is terminated with split response, the master would wait for the split completion transfer from the target.
The target controller is capable of handling memory and IO accesses on the PCI and PCI-X bus. All memory/IO accesses are supported. Configuration register read and write transactions are supported locally by the bus target without assistance from the user logic. Memory and I/O write to the target are posted in the write buffer before they are transferred to the user. Memory and I/O read are handled as delay read on PCI bus and as split transaction on PCI-X bus. The user interface allows the user to control the characteristics of the access. For example, the user can insert a wait state or transfer data without wait state according to its data bandwidth.
As a host bridge, this PCI-X IP is also capable of initiating PCI and PCI-X configuration access on the bus. This feature allows the host CPU to initiate the bus system during system power up. The PCI-X core contains the CONFIG_ADDR and CONFIG_DATA registers and address decoding circuitry so that the standard PCI configuration mechanism can be used.
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