64-bit PCI-X Master/Target

Features

• Fully supports PCI and PCI-X protocol.
• Designed for ASIC and PLD implementations.
• Fully static design with edge triggered flip-flops.
• Efficient user interface for different types of user devices.
• User interface and PCI interface runs at different clock speed.
• Include data buffer and synchronization logic to bridge the two clock domains.
• Automatic detection of PCI and PCI-X bus systems.
• Combined bus master and target functions.
• Master function
• Initiate PCI memory and IO read/write.
• Automatic transfer restart on target retry and disconnect.
• Target function
• Memory or IO read/write.
• Configuration read/write.
• Split transaction.
• Supports Zero wait state and user inserted wait state burst data transfer.
• Dual write buffer in each direction to support write data posting.
• Automatic handling of configuration register read/write access.
• Parity generation and parity error detection.
• Includes all PCI specific configuration registers.
• Supports high speed bus request and bus parking.