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64-bit RISC-V Application Processor Core
The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC.
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.
Tensor Flow Lite Micro is supported
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.
Tensor Flow Lite Micro is supported
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Block Diagram of the 64-bit RISC-V Application Processor Core IP Core
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- 32-bit Embedded RISC-V Functional Safety Processor
- Dual-issue Linux-capable RISC-V core