LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
65nm LP 2.5V/1.2V 11bit 2.5Mhz R2R DAC [1ch]
resolution. The sampling rate is up to 5M samples per second. The IGADACR03A is
composed of an R-2R resistive ladder and a voltage buffer.
Supply voltage 2.5V is used for analog devices and high-voltage logic devices in the
DAC circuit and 1.2V is used for core-voltage logic devices. Output voltage of
IGADACR03A is single ended with rail-to-rail range. The IGADACR03A exhibits excellent
monotony with low DNL/INL. A power down mode is available to disable the DAC and lower
down the power consumption.
The IGADACR03A is fabricated in TSMC 65nm 2.5V/1.2V CMOS process with 1P7M
layout. There is a test chip available in LQFP64 package; the corresponding part number is
UR0084A.
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