MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
8-Bit Microprocessor Core
The 8-bit data bus based architecture provides a flexible interface to memories, peripherals and other IP blocks.
WDC's RTL Softcore version provides a cycle accurate option providing for implementation onto any foundry process.
Development tools are available for creation of 65xx application code.
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