Multiplying Delay-Locked Loop - TSMC 90 nm

The Multiplying delay-locked loop (MDLL) clock multiplier accept an input clock and generates a phase-locked output clock at a multiple of the input clock frequency. As with a DLL, each rising edge of the input clock zeros the phase error of the loop. Hence this circuit combines the low phase noise of a DLL with the clock multiplication ability of a PLL. A divide-by-M counter provides a programmable multiplication ratio for the MDLL.

• see the entire 800/1000 MHz DLL-based frequency multiplier datasheet
• get in contact with 800/1000 MHz DLL-based frequency multiplier Supplier