Aeonic Generate Digital PLL for multi-instance, core logic clocking
800G Ethernet IP for AI Application
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Block Diagram of the 800G Ethernet IP for AI Application
Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E)
- 112G Ethernet PHY in TSMC (N7, N5, N3P)
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency