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800MHz LVDS Cell Set for 180nm
The OT3910 is a set of cells for implementing 800Mb DDR (400MHz) LVDS IO in 180n CMOS processes.
Includes transmitter and receiver IO's. Also core based bias cell.
An evaluation board and test chip are available. The chip has built in BER testing. Key IO signals are available on coax headers.
Includes transmitter and receiver IO's. Also core based bias cell.
An evaluation board and test chip are available. The chip has built in BER testing. Key IO signals are available on coax headers.
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Block Diagram of the 800MHz LVDS Cell Set for 180nm
LVDS IP
- TSMC GF LVDS Tx/Rx with optional CMOS I/O
- TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF