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AV1/HEVC/AVC/VP9 Video Codec HW IP

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

Low Noise, High PSRR Replica Voltage Regulator

• Power Supply : 1.8 V
• Output voltage : 1.2 V
• Quiescent current: 7.3 mA

LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X

• Complete, integrated LPDDR5X/5/4X solution from a single vendor when combined with Synopsys’ LPDDR5X/5/4X PHY IP

KYBER IP Core

• supports encapsulation and decapsulation operations
• supports all modes K=2,3,4.
• is compliant with Kyber specification round 3.

High-efficiency vector DSP cores for 5G and 5G-Advanced

• True dual-threaded hardware, including dual processing elements and dual instruction and data memory subsystems for contention-free multithread execution

UCIe D2D Adapter

• Ultra Low Latency
• CRC and Retry, or Parity Computation
• Multiple Protocols,

11-bit, 5 GSPS Analog-to-Digital Converter

• 11-bit resolution
• 5 GSPS sampling rate
• 6 GHz Input Bandwidth

RT-7xx CryptoManager Root of Trust

• Secure co-processor
• Main processor agnostic
• Standard secure applications

CXL 3 Controller

• Supports configuration of PCIe vs CXL protocol mode
• Supports both RC and EP modes

PCIe 4.0 PHY IP for SS 14LPU

• Physical Coding Sublayer (PCS) block with PIPE interface
• Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

On-Chip IO to Core Voltage Buck Regulator

• Input voltages of 2.5V, 3.3V.
• Available output currents to 100mA.

LPDDR5 IP - High performance and low power

• Support LPDDR5 up to 6400Mbps
• Support Channel equalization with 1-tap DFE

Smart Network-on-Chip (NoC) IP

• Smart NoC automation
• Topology generation with minimum wire length
• Scripting-driven regular topology creation

12-bit, 9.2 GSPS Analog-to-Digital Converter

• 12-bit Resolution
• 9.2 GSPS Sampling Rate
• 6 GHz Input Bandwidth

3GPP LTE Turbo Encoder

5G LDPC Encoder / Decoder

• CRC encoding
• Filler bits insertion/removal
• LDPC encoding (basegraph1 and 2, all Z-values)

5 GHz 250 fs jitter Phase Locked Loop IP Block

• Input Frequency: ~100MHz
• Output Frequency: 5 GHz
• RMS Jitter: <250 fs
• Supply Voltages: 0.8 V (Core), 1.8V (IO)

LDPC Encoder / Decoder

• Full hardware
• performance/gatecount
• configurable generator matrix

TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

SerDes Hard Macro-IP in GlobalFoundries 22FDX

• Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

LTE turbo decoder

• Covers rate-matching, turbo decoding and CRC decoding
• Throughput level 75 to 300 Mbps