Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The required voltage for OTP bit cell programming can ...

Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The required voltage for OTP bit cell programming can ...

Rambus PCIe 5.0 Multi-port Switch is a customizable, Embedded PCIe Switch designed for ASIC and FPGA implementations enabling the connection of one upstream port and multiple downstream ports ...

The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI slave/master interfaces, APB port ...

The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory. It supports AXI slave/master interfaces, APB port for configuration purpose. ...

A 2.5G GSM/GPRS/EDGE SW Protocol Stack that has been integrated with multiple basebands and shiped in 1bn phones and M2M modules world wide. Extensively field trialed, extremely modular, and ...

This Bluetooth Dual Mode (BTDM) Software Stack is the most mature and widely used licensed SW Stack in the market for Bluetooth Audio (Dual Mode) and IOT (Low Energy) products today. The stack ...

Evaluation Package Available

This NB-IoT Protocol Stack is 3GPP Release 17 compliant, Access Stratum and Non-Access Stratum (L2-L3 layers) which are further upgradable to future Releases. The NB-IoT software is highly configurable ...

The DisPlay Port/HDMI/DVI Receiver is a high performance combo PHY with Display Port Receiver and HDMI Receiver. In DisPlay Port mode, the receiver is VESA DP1.1a, DP1.2 and eDisPlay Port compliant ...

USB 1.1 Device Controller IP is based on the latest USB 1.1 specification from USB Implementer Forum (USB-IF) and is compatible with the latest xHCI 1.1 specification. It supports FullSpeed ...

Bluetooth Dualmode Software IP includes versions v5.0,and below, of Bluetooth Smart & Bluetooth Smart Ready Stack & Profiles. EtherMind is a comprehensive offering which consists of all the ...

Consumer Multimedia Applications: Wide support of Consumer PHY standards such as PCIe Gen1/2/3, USB 3.0 Super Speed, JESD204B, SATA Gen 1/2/3 and SGMII / QSGMII from 1.125 Gb/s to 8Gb/s / 10 ...

Audio Weaver® an Audio SW Development Platform, an Audio drag and drop EDA suite if you like, to streamline the audio algorithm SW development process by you and your customers on your chipsets. ...

This is a 3GPP 5G NR Release 16 Compliant g-NodeB solution. The solution adapts a modular Design with the clear interface between the various modules supporting various RAN functional splits. ...

IP core that completely conforms with HDMI 1.4 requirements for physical layer HDMI transmitters For consumer electronics like DVD player/recorders and camcorders, the HDMI transmitter PHY offers ...

A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers and supports up to 1.5Gbps data rate. The input clock is 25MHz to 150MHz. The serializer is highly ...

This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to DVB-S, legacy DirectTV, DVB-S2 and DVB-S2X specifications. The ...

Our IP is Fully compliant with 2.4GHz IEEE 802.11ax(WIFI 6) and Bluetooth standards, this WiFi 802.11 ax(WiFi ax)/Bluetooth LE v5.4/15.4, 2.4GHz RF Transceiver IP is available in TSMC22ULL(Ultra-low ...

The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog simulation software using test bench written ...

The combined PHY complies with the Peripheral Component Interconnect Express (PCIe), Serial ATA, USB, USB 3.0, and USB 2.0 interface protocols (USB High-speed and Full speed). Reduced power ...

The LC3plus audio codec is a highly optimized and highly efficient audio codec introduced for Bluetooth LE Audio, DECT and VoIP that dramatically improves streaming audio quality, reduces power, ...

The NTN System Test Bench (STB) is a cost-effective, flexible environment for NTN satellite network operators or applications developers. Simulating either transparent or regenerative modes ...

The NB-IoT NTN System Test Bench (STB) is a cost-effective, flexible testing environment for NB-IoT NTN eNodeB product developers. Simulating either transparent or regenerative modes for LEO ...

This 8051 IP core implements a range of fast, 8-bit, 8051-compatible microcontrollers that execute the MCS®51 instruction set. The R8051XC2 IP core runs with a single clock per machine cycle, ...

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Matt Jones, VP of Strategic Marketing, Rambus

Harmony Trace by Arteris, the innovative Design Data Intelligence Solution for complex SoC and System-of-SoCs projects. Accelerate quality and functional safety certifications effortlessly with ...

Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommunications, embedded systems, high performance peripheral cards, ...

Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommunications, embedded systems, high performance peripheral cards, ...

Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommunications, embedded systems, high performance peripheral cards, ...

Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC introduces controlled redundancy in the data before it is transmitted to allow error correction at the receiver. The ...

Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC introduces controlled redundancy in the data before it is transmitted to allow error correction at the receiver. The ...

Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommunications, embedded systems, high performance peripheral cards, ...

The Lattice SGMII and Gb Ethernet PCS IP core implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX) specifications. The PCS mode is pin selectable. This IP core ...

The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR SDRAM. The memory controller ...

The Lattice 2.5 Gbps Ethernet PCS IP core implements the state machine functions for the physical coding sublayer (PCS) described in the IEEE 802.3z (1000BaseX) specification. Note that the ...

This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined version. DDR (Double Data Rate) SDRAM was introduced as a replacement ...

Overview The DDR3 Pinout Generation Utility is a GUI tool that is capable of generating the pinout and preference files that contain information for a design that uses the DDR3 SDRAM ...

A Finite Impulse Response (FIR) filter performs a convolution of an input data sequence with the filter's impulse response (the discrete-time inverse Fourier transform of its desired frequency ...

Median filtering is a popular method of noise removal, employed extensively in applications involving speech, signal and image processing. This non-linear technique has proven to be a good alternative ...

Intel defined the PHY Interface for PCI Express (PIPE) as a standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications. The PIPE interface allows ...