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Fences 4 stardock IP Listing

8990 IP Cores (1 - 40)

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200G and 400G Ethernet PCS IP

The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a complete set of features that enable users to define an optimized ...

1
The Synopsys 1.6T Ethernet MAC IP is based on IEEE 802.3-2018 spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications

The Synopsys 1.6T Ethernet MAC IP implements the functions required by the IEEE 802.3-2018 specification to communicate over Ethernet providing a simple frame-based interface to the system and ...

2
1.6T Ethernet PCS IP based on the IEEE 802.3dj spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications

The Synopsys 1.6T Ethernet PCS IP is based on the concepts of the evolving draft IEEE 802.3dj standard creating a flexible system solution for next generation 400Gbps and 800Gbps and 1.6Tbps ...

3
Multi-Protocol Crypto Packet Engine, Low Power, Bus Attached

The EIP-93 is a Multi-Protocol Engine. The EIP-93 is designed to off-load the host processor to improve the speed of protocol operations and reduce power in cost-sensitive networking products, ...

4
Multi-Protocol Crypto Engine

The EIP-97 is a Cryptographic Engine designed to offload the Host processor to improve the speed of IPsec ESP, IPsec AH, SRTP, SSL, TLS, DTLS and MACsec protocol operations and reduce power ...

5
Multi-Protocol Crypto Engine with Classification

The EIP-197 is a family of high speed Cryptographic Accelerators with embedded Classification Engine, Virtualization, Latency compensation to maintain performance under stress conditions in ...

6
LPDDR Combo Controller - LPDDR4X/4 & LPDDR5T/5X/5

The Rambus LPDDR4 and LPDDR5 combo controller core is designed for use in applications requiring high memory throughput at low power including mobile, Internet of Things (IoT), automotive, laptop ...

7
MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

Arasan delivers you MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing ...

2 Testimonials
David Moloney, Chief Technology Officer at Movidia, Movidia

8
SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller

The eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and I/O technologies: 1) SD, 2) SDIO and 3) eMMC memory formats. ...

9
MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

Arasan's MIPI C-PHY is designed and compliant with latest MIPI C-Phy Standards. The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited channel, allowing more data without an increased ...

10
MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.2 improves throughput over a bandwidth limited channel, allowing more data without increased signaling clock. It is intended ...

11
USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm

The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use with host, embedded host, On-the-Go (OTG) ...

12
USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm

The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use with host, embedded host, On-the-Go (OTG) ...

13
ONFI 4.2 Controller

Arasan Chip System’s (ACS) Open NAND Flash Interface (ONFI) Host Controller is designed to provide the next generation of high speed interaction with ONFI compliant NAND ﬂash chips. Compared ...

14
Securyzr iSE S700 neo series by Secure-IC: an integrated Secure Element (iSE) for automotive

As part of Secure-IC's iSSP (integrated Security Service Platform), Secure-IC is able to provide integrated Secure Elements (iSE) that can act as trust anchors that protect the security assets ...

15
TSMC CLN4P 4nm DDR5 PHY - 6400Mbps

The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. ...

16
TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL

High-bandwidth, De-Skew Frequency Synthesizer for minimizing clock tree timing uncertainty. See our features list for more details.

17
TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL

Widely programmable fractional-N delta sigma frequency synthesizer with industry leading jitter performance. See our features list for more details.

1 Testimonial
Kazuhisa Sasaki, General Manager, Development Department, THine Electronics, Inc.

18
TSMC GF Intel Samsung Integer-N Frequency Synthesizer PLL

Widely programmable integer-N frequency synthesizer with industry leading jitter performance and flexible power options. See our features list for more details.

19
TSMC Intel 32kHz Low-bandwidth Frequency Synthesizer PLL

Low-bandwidth, Ultra-Fast-Lock Frequency Synthesizer, capable to operate with a very low reference frequencies (32kHz - 33kHz). See our features list for more details.

1 Testimonial
Andreas Papaliolios, Director, IoT Silicon Technology, Architecture, and Design, Renesas USA

20
Low-Latency SerDes PMA - 10GbE, 25GbE

Best(lowest)-in-class latency 10GbE/25GbE SerDes PMA.

21
Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

Multiprotocol SerDes PMA supporting variety of interfaces.

1 Testimonial
Lyle Smith, Vice President of Product Development Engineering, Microsemi SoC BU

22
MIPI C-PHY/D-PHY Combo RX+ IP (4.5Gsps/4.5Gbps) in TSMC N5

The MXL-CD-PHY-CSI-RX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0. The PHY can ...

23
MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6

The MXL-CDPHY-6p0G-CSI-2-RX+-T-N6 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0. The PHY ...

24
TSMC GF LVDS Tx/Rx with optional CMOS I/O

Flexible I/O cell for data and clock applications that supports differential (and optionally single-ended) Tx and Rx capabilities with no external components required. See our features list ...

25
TSMC Crystal Oscillator (XTAL)

Universal, Mems- or Crystal-resonator compatible on-chip XO is a baseline for quality clock generation system. See our features list for more details.

26
TSMC Samsung GF Free-Running Oscillators

Low power relaxation oscillator is a programmable free-running clock generator for coarse clock generation. The design uses a relaxation oscillator with fully integrated elements so no external ...

27
TSMC Samsung GF Intel CML mux - on-chip clock buffer

Distribute high-performance clock across your chip with reduced supply-noise coupling. See our features list for more details.

28
TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

29
Ceva-Waves Bluetooth 5.4 Low Energy Baseband Controller / Link Layer, software and profiles

Ceva-Waves Bluetooth 5.4 Low Energy IP is a comprehensive and flexible solution for integration into SoCs/ASSPs. The Ceva-Waves BLE hardware baseband controller core, in charge of packet ...

30
IPsec - Security Protocol

IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec core enhances secure communication at layer three (Network) ...

31
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency

Lowest latency in market ; Ultra low latency FEC and SERDES combo ; Provides sub 10ns combined latency ; Best in Class BER ; Support VSR, MR and LR

32
UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect

Blue Cheetah is a leader in Die-to-Die (D2D) interconnect solutions for chiplets in very advanced and low-cost packaging applications. BlueLynx™ is a revolutionary D2D subsystem architecture ...

33
Ceva-Waves Bluetooth 5.3 Low Energy Baseband Controller, software and profiles

Ceva-Waves Bluetooth 5.3 Low Energy IP is a comprehensive and flexible solution for integration into SoCs/ASSPs. The Ceva-Waves BLE hardware baseband controller core, in charge of packet ...

34
4K/ 8K LCEVC Video Decoder

AL-D301 is Allegro DVT’s LCEVC decoder IP core which provides support for the LCEVC video format. It operates in combination with a base layer decoder, decoding the LCEVC enhancement layer ...

35
4K/ 8K LCEVC Video Encoder

AL-E301 is Allegro DVT’s LCEVC encoder IP core which provides support for the LCEVC video format. It operates in combination with a base layer encoder, encoding the LCEVC enhancement layer ...

36
Video Encoder IP – 4k60 Scalable up to 8K120

The E300 Series, a new generation of video encoder IPs built upon a higher performance architecture with support for resolutions from 4K60 up to 8K120. The E300 Series of encoder IPs implements ...

37
Video Encoder IP - 4k60 Scalable up to 8K120

The new E320 Encoder IP is the latest addition to Allegro DVT’s E300 series, it supports multiple video formats by sharing resources between H.264, HEVC, VP9, AV1 and the newly added VVC compression ...

38
PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

2 Testimonials
Serge Leef, Microsystems Technology Office Program Manager, DARPA

39
PCIe 5.0 Controller with AMBA AXI interface

Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controller is compliant with the PCI Express 5.0 ...

1 Testimonial
Russel Lindsay, Sr. Product Manager, Anritsu Corporation

40

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