level 2 cache controller with axi interface IP core / Semiconductor IP / Silicon IP

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Level 2 cache controller with axi interface IP Listing

AXI System Cache

MIPI LLI Controller - (Low Latency Interface)

32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications

RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications

ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications

ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)

ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications

ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications

32-Bit SPARC V8 Processor

32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN

64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN

32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)

32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux

64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux

Arm Cortex-A7

32-bit RISC-V core with in-order single issue pipeline for Linux-based systems

64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems

64-bit RISC-V core with out-of-order pipeline based complex for Linux-based embedded systems

64-bit RISC-V microcontroller. Small core for 64-bit applications.

64-bit High performance Dual Core Microprocessor

64-bit High performance Quad Core RISC-V Microprocessor

64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems

32-bit RISC-V microcontroller. Leading performance in class with optimized power consumption and area

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