This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run around 100MHz. By setting different values of DM(4:0) and DN(5:0) according to different ...

Present IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 150MHz to 266MHz. By setting different values of DM(4:0) and DN(5:0) according to ...

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 300MHz to 600MHz. By setting different value of DM(4:0) and DN(6:0) according to different ...

This PLL is designed for audio clock generation. The reference clock is 12MHz crystal or input clock. It supports 256*fs clock output, here fs is audio system sample rate of 32kHz/44.1kHz/48kHz. ...

This IP is a programmable Analog PLL suitable for high speed clock generation. Its high speed VCO can run from 60MHz to 160MHz. The output frequency is from 30MHz to 80MHz. By setting PLL_DM ...

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting DM(5:0) and DN(6:0) to different values according to different ...

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 300MHz to 600MHz. By setting DM[4:0] and DN[6:0] to different values according to different ...

The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives data via DP and DM and transfers data to USB1.1 ...