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Processor memory bus interface IP Listing

275 IP Cores (1 - 40)

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I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)

The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard ...

1
I2C Master / Slave Controller w/FIFO (APB Bus)

The I2C Master / Slave Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, ...

2
SSL/TLS Processor IP Core with an AXI Bus Interface

The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of system through two AXI interfaces: ...

3
I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)

The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard ...

4
Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support

The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interface directly with numerous standard product ...

5
Local Memory Bus (LMB)

The LMB module is used as the LMB interconnect for Xilinx FPGA based embedded processor systems. The LMB is a fast, local bus for connecting MicroBlaze™ instruction and data ports to high-speed ...

6
Secure-IC's Securyzr™ Memory & Bus Protection IP Core

The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory. It supports AHB/AXI slave/master interfaces, APB port ...

7
Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support

The DOSPI is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interface directly with numerous standard product ...

8
SPI Master / Slave Controller w/FIFO (APB Bus)

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface ...

9
eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)

The Digital Blocks DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave ...

10
Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support

The DQSPI is a revolutionary quad SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interface directly with numerous standard product ...

2 Testimonials
Alex Chen, Project Leader of Business Project Department, Faraday Technology Corporation

11
AHB External Bus Interface

The AHB External Bus Interface (EBI) allows a CPU or AHB Master (such as a DMA core) to transmit and receive data to an external device such as an external SRAM or Parallel Flash device. ...

12
SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface ...

13
SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface ...

14
SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)

The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex). The DB-SPI-M contains an ...

15
SPI Master Controller w/FIFO (APB Bus)

The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex). The DB-SPI-M contains an ...

16
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA

The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash Memory devices by way of Boot, Execute-in-Place ...

17
AMBA AHB-Lite Bus Interface

CoreAHBLite is a multi-master implementation of the AHB-Lite bus interconnect (a subset of the AMBA advanced high-performance bus) used to connect subsystem cores to Microsemi's 32-bit ARM processors. ...

18
High performance interface for SD/MMC memory cards

CoreMMC provides a MultiMedia Card (MMC) controller to interface with external MMC flash cards and eMMC devices. The CoreMMC controller allows you to store theboot images and boot the processor ...

19
CAN 2.0, CAN FD & CAN-XL Bus Controller

Implements a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications. It supports the original Bosch protocol and ISO specifications ...

5 Testimonials
Yusuke Awano, Senior Engineer, DTS Insight Corporation

20
AXI Bus Display Controller

The Digital Blocks DB9000AXI3 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a LCD or OLED display panel. The Display ...

21
Display Controller - LCD / OLED Panels (AXI Bus)

The Digital Blocks DB9000AXI LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a LCD or OLED display panel. ...

22
Display Controller - LCD / OLED Panels (AXI4 Bus)

The Digital Blocks DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protocol Interconnect to a LCD or OLED display panel. ...

23
LPDDR4x/5 Secondary/Slave (memory side!) PHY

This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/LPDDR5 combo IP provides the unique opportunity ...

24
LPDDR4x Secondary/Slave (memory side!) PHY

This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X IP provides the unique opportunity to transmit ...

25
LPDDR5 Secondary/Slave (memory side!) PHY

This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5 IP provides the unique opportunity to transmit ...

26
LPDDR5X Secondary/Slave (memory side!) PHY

This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5X IP provides the unique opportunity to transmit ...

27
Ultra-Low-Power Deeply Embedded RISC-V Processor

The BA51 is a highly configurable, low-power deeply embedded RISC-V processor IP core. It implements a single-issue, in-order, 2-stage execution pipeline, supporting the RISC-V 32-bit base integer ...

1 Testimonial
Hugh O’Keeffe, CEO, Ashling

28
RISC-V Application Processor

The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V is designed for space applications: with its high-performance and fault-tolerant design, ...

29
32-Bit SPARC V8 Processor

The LEON4 processor core is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The core is highly configurable and particularly suitable for high performance ...

30
RISC-V Processor - RV12 - 32/64 bit, Single Core CPU

The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based ...

Try this IP for Free!

31
32-Bit SPARC V8 Processor

The LEON5 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and suitable for system-on-chip (SOC) designs. LEON5 ...

32
Tensilica Xtensa LX Processor Platform

Versatile 32-bit RISC processor with configurable 5/7-stage pipeline addressing a wide range of application requirements ranging from a tiny cache-less controller to a high-performance DSP ...

33

Tensilica Xtensa NX Processor Platform

32-bit RISC processor with 10-stage pipeline offers performance of over 2GHz suitable for embedded applications with high performance, large memories, and compute-intensive requirements ...

34

32-bit SPARC V8 processor

The LEON3 processor is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 acrhitecture. The model is highly configurable, and particularly suitable for system-on-a-chip ...

Download the GPL version of LEON3/GRLIB

35

64-bit RISC-V Multi-Core Linux-Capable processor

The U5 Series features a RISC-V Linux-capable application processor that offers high performance with maximum efficiency. The U5 core has a 5-6 stage pipeline and supports virtual memory, enabling ...

36

High performance 32-bit RISC-V Processor

37

PowerVR Series8XE Graphics Processor

High-performance for entry-level markets The PowerVR Series8XE family of GPUs drives cost reduction in entry-level and mass market devices thanks to a design that has been optimised to deliver ...

38

PowerVR Series8XE Plus Graphics Processor

Series8XE Plus GPUs available in a range of configurations Available in two- and four-cluster configurations, Series8XE Plus is designed specifically to deliver the right mix of performance, ...

39

PowerVR Series8XT Graphics Processor

The PowerVR Series8XT family is based on the new Furian GPU Architecture and pushes mobile and embedded performance to new heights with configurations featuring 2 to 8 clusters offering dramatically ...

40

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