The DDR PHY IP supports DDR5/ DDR4/ LPDDR5, provides low latency, and enables up to 5400MT/s throughput. PHY functionality is verified in NC-Verilog simulation software using test bench written ...

Synopsys SLM SMS IP is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or non-repairable embedded memories across any foundry or process node. Silicon-proven ...

Synopsys SLM STAR ECC 6 IP is a stand-alone product used to mitigate against soft errors in memories with the goal of improving in-field reliability

This memory controller supports DDR3/4 SDRAM. DDR3/4 memory controller is a high-speed interface used for data read/write between internal engine and outside SDRAM bus, and transfers the internal ...

This DDR PHY IP(Double Data Rate) supports DRAM type DDR3, DDR3L this PHY provides low latency, and enables up to 1600Mbps throughput. The DDR IP is compliant with the latest JEDEC standards ...

The DDR3L/ DDR4/ LPDDR4 Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the UMC 28HPC+ process technology, complies with the most ...

This DDR (Double Data Rate) PHY IP supports DDR3/DDR3L/DDR4, provides low latency, and enables up to 1600Mbps throughput. The PHY IP is silicon proven and designed for ease of integration and ...

The DDR4/3 PHY is compatible with JEDEC DDR3 and JEDEC DDR4 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to 2133Mbps and DDR4 DRAM speeds from 1866Mbps to 2400Mbps, and target support ...

The DDR (Double Data Rate) controller IP is for LPDDR4 and DDR4/3/3L optimized for low latency. The Controller IP is silicon proven and connects to DDR PHY via the DFI 4.0 interface to provide ...

The DDR3/2 PHY is compatible with JEDEC DDR3 and JEDEC DDR2 SDRAMs, supports a range of DDR3 DRAM speeds from 666Mbps to1866Mbps and DDR2 DRAM speeds from 666Mbps to 1066Mbps, and target support ...

This memory controller supports DDR2/3 SDRAM. DDR2/3 memory controller is a high-speed interface used for data read/write between internal engine and outside SDRAM bus, and transfers the internal ...

The DDR4/ DDR3L/ LPDDR4 Combo PHY IP provides low latency and enables up to 3200Mbps throughput. The PHY IP is compliant with the latest JEDEC standards and is silicon proven in TSMC 12FFC process ...

The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the TSMC 28HPC+ process technology, complies with the most ...

The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the TSMC 28HPC+ process technology, complies with the most ...

This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/LPDDR5 combo IP provides the unique opportunity ...

This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X IP provides the unique opportunity to transmit ...

This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5 IP provides the unique opportunity to transmit ...

This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5X IP provides the unique opportunity to transmit ...

RAAAM’s Gain-Cell RAM (GCRAM) is the most cost-effective on-chip memory technology in the semiconductor industry. GCRAM combines the density advantages of embedded DRAM with SRAM performance, ...

The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the memory subsystem. The cache controller ...

The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The encoder core has a small silicon footprint—approximately ...

The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master ...

SkyeChip’s High Bandwidth Memory (HBM) IP consists of a PHY and memory controller optimized for TSMC N7, N12 and Samsung 4nm process to support the HBM3 memory standard operating at up to ...

ComputeRAM is an SRAM macro with integrated compute capability. It is a semiconductor IP product designed to enable microcontroller-based systems to run AI, DSP, and other linear algebra routines ...

Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit. The phenomenon first became an issue in DRAM, requiring error detection ...

Fast Cycle RAM (FCRAM) is a DRAM technology with a specialized memory core technology that achieves faster random access times and offers lower power consumption than traditional DRAMs. FCRAM ...

Our IP Core enables you to create chips for automotive nn acceleration with excellent sustained performance and low power under real workloads The aiWare hardware IP Core is highly customizable ...

Industry-Leading Performance and Efficiency for Inference at the Edge Based on a new, class-leading architecture, the Arm ML processor’s optimized design enables new features, enhances ...

Optimized for the most cost- and power-sensitive designs, Ethos-N57 delivers premium AI experiences in mainstream phones and digital TVs. The Arm AI platform makes it easy to develop on Arm ...

Build low cost, highly efficient AI solutions in a wide range of embedded devices with Arm’s latest addition to the Ethos-U microNPU family. The Ethos-U65 maintains the power efficiency of ...