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St louis apartments for rent IP Listing

10281 IP Cores (1 - 40)

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UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

1
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

2
MACsec Engine, 1G to 25G, Full Duplex, Integrated

As part of Rambus' award-winning silicon Intellectual Property (IP) product portfolio, the EIP-165 is a high-performance, split ingress/egress in-line MACsec frame engine that provides hardware ...

3
VESA DSC (Display Stream Compression) 1.2b Video Encoder

VESA DSC 1.2b compliant ; Supports all DSC 1.2b mandatory encoding mechanisms ; MMAP, BP, MPP, and ICH ; Output buffering compatible with transport stream over video interfaces ; Configurable ...

4
VESA DSC (Display Stream Compression) 1.2b Video Decoder

VESA DSC 1.2b compliant ; Supports all DSC 1.2b mandatory encoding mechanisms ; MMAP, BP, MPP, and ICH ; Input buffering compatible with transport stream over video interfaces ; Configurable ...

5
ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder

The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to detect and report transient or permanent ...

6
VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs

Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC) ; Fully compliant with the DisplayPort 1.4a Standard ; Including the DSC slices per line ...

7
IPsec software toolkit

The Rambus IPsec Toolkit (previously QuickSec from Inside Secure) is client/server software for cloud and embedded security. It provides a complete software stack to build scalable IPsec VPN ...

8
VESA DisplayPort 2.0 FEC RX

The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 2.0 specification. Forward Error Correction ...

9
MACsec Engine, 1G to 100G Single-Port

The MACsec-IP-160 is a versatile MACsec solution for silicon devices that require plug-and-play MACsec processing for an Ethernet port at full line rate. It provides classification, transformation ...

2 Testimonials
Hweihn Chung, CTO, NextChip

10
ICE-IP-338 High-speed XTS-GCM Multi Stream Inline Cipher Engine

The Protocol-IP-338 (EIP-338) is a scalable, high-performance, multi-stream cryptographic engine that offers XTS and GCM modes of operation for the AES algorithms on bulk data. Its flexible ...

11
ICE-IP-358 High-speed XTS-GCM Multi Stream Inline Cipher Engine, DPA resistant

The Protocol-IP-338 (EIP-338) is a scalable, high-performance, multi-stream cryptographic engine that offers XTS and GCM modes of operation for the AES algorithms on bulk data. Its flexible ...

12
Fractional-N Integer LC DESKEW PLLs in FDSOI FDX (GF22FDX SS28FDS ST28FD-SOI 22FDX 28FDS)

Widely programmable frequency synthesizers with industry leading jitter performance.

13
MACsec - Extreme-speed - Security Protocol

MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards the confidentiality and integrity of data ...

14
Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium)

The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum computing. This IP core is engineered to provide ...

15
Post-Quantum Cryptography - nQrux® Secure Boot - Quantum-Secure Authenticated Boot (PQC)

nQrux® Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrity of binary images during the processor boot sequence. ...

16
eFPGA IP - 100% third party standard cells

For ASIC and SoCs designers who need fast, right-the-first time design and fast time to volume, Menta is unique in our ability to deliver proven eFPGAs in your selected technology for your specific ...

17
UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect

Blue Cheetah is a leader in Die-to-Die (D2D) interconnect solutions for chiplets in very advanced and low-cost packaging applications. BlueLynx™ is a revolutionary D2D subsystem architecture ...

18
The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.

SuperFlash® is SST’s patented and proprietary NOR flash technology. With 80B+ devices shipped, SuperFlash is the non-volatile memory of choice for embedded applications. In high-volume production ...

19
Bluetooth low energy v6.0 Baseband Controller, Protocol Software Stack and Profiles IP

This Software and Silicon IP solutions, feature Bluetooth v6.0 capabilities including a certified Link-layer controller, Digital PHY, Stack & Profiles. Endorsed by the Bluetooth Special Interest ...

20
Tessent Status Monitor

The Tessent Embedded Analytics Status Monitor provides visibility and monitoring of any circuitry within a System-on-Chip (SoC). It affords many of the benefits of a logic analyzer, but with ...

21
Tessent Static Instrumentation

The Tessent Embedded Static Instrumentation module provides a nonintrusive mechanism for code instrumentation. Software engineers can insert watchpoints in the code that trigger messages on ...

22
Secure-IC's Securyzr™ Tunable AES (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection

The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data established by the U.S National Institute of Standards and Technology (NIST) in 2001. It is included ...

23
12bit 5Gsps silicon proven High performance Current Steering DAC IP Core

The 12-bit 5 GSPS DAC IP Core employs a high-performance current steering architecture and provides an optional differential current output or differential voltage output. The bandgap and current ...

24
SinglePHY 100BASE-T1 22FDX

SinglePHY 100BASE-T1 22FDX is a fully integrated 100BASE-T1 PHY IP solution for flexible customer SoC integration in GLOBALFOUNDRIES® 22FDX®.

25
DualPHY 100/1000BASE-T1 22FDX

DualPHY 100/1000BASE-T1 22FDX is a fully integrated 100/1000BASE-T1 PHY IP solution for flexible customer SoC integration in GLOBALFOUNDRIES® 22FDX®.

26
40G UCIe PHY for organic substrate standard packages

Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY’s ...

27
MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables

Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is available on both TSMC’s industry-leading ...

28
Bluetooth low energy v5.4 Baseband Controller, Protocol Software Stack and Profiles IP

This Software and Silicon IP solutions, feature Bluetooth v5.4 capabilities including a certified Link-layer controller, Digital PHY, Stack & Profiles. Endorsed by the Bluetooth Special Interest ...

29
Open RAN Platform for Base Station and Radio

Industry’s First Comprehensive 5G Baseband Platform IP for 5G RAN ASICs and Open RAN Building on more than a decade of leadership in baseband IP solutions, in mass production in Tier 1 OEM ...

30
Hardware 8-bit/12-bit JPEG Codec IP

Chips&Media CODAJ12V is a standalone and high-performance JPEG codec IP that can perform JPEG Baseline/Extended and MJPEG decoding and encoding. Compliant with the Extended sequential DCT ...

31
Lossless & Near-Lossless JPEG-LS Encoder

The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard. Based on LOCO-I ...

32
Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard

The BitCsi2Rx IP is a receiver for camera sensor signals, to be used in an FPGA or ASIC. It receives camera signals in accordance with the MIPI CSI-2 and D-PHY specifications. BitCsi2Rx converts ...

33
nQrux® Crypto Module

Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, suitable for both microcontrollers and ...

34
16bit 5Gsps silicon proven High performance Current Steering DAC IP Core

16-bit 5GSPS DAC IP Core utilizes a high-performance current steering design and offers the option of either a differential current output or a differential voltage output. It includes a bandgap ...

35
AES-GCM Authenticated Encrypt/Decrypt Core

The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, ...

36
Secure-IC's Securyzr(TM) Crypto Coprocessor (Standard)

The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC. Symmetric operations are offloaded ...

37
SONET/SDH: OC12/4xOC3|STM-4/4xSTM-1 Framer

The SONET/SDH OC12/4xOC3 & STM-4/4xSTM-1 Framer core implements the STS-12/4xSTS-3 and STM-4/4xSTM-1 layer function of Telcordia GR-253-CORE/ITU-T G.707, supporting data rate at 622M/s. In ...

38
SONET/SDH: OC192/STM-64 Framer

The SONET/SDH Concatenated/Non-concatenated STS-192/STM-64 core implements the STS-192 and STM-64 layer function of Telcordia GR-253-CORE/ITU-T G.707, supporting data rate at 10G/s. In the ...

39
SONET/SDH: OC48/STM-16 Framer

The SONET/SDH Concatenated/Non-concatenated STS-48/STM-16 core implements the STS-48 and STM-16 layer function of Telcordia GR-253-CORE/ITU-T G.707, supporting data rate at 2.5G/s. In the ...

40

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