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Susunan lencana di abju untuk pengakap kelana IP Listing

8334 IP Cores (1 - 40)

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HDCP 2.3 Embedded Security Modules on DisplayPort/USB Type-C

The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide designers with a robust, standards-compliant implementation ...

1
VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver

The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction ...

2
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter

The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction ...

1 Testimonial
Neal Kendall, Product Manager, Teledyne LeCroy

3
VESA DSC (Display Stream Compression) 1.2b Video Encoder

VESA DSC 1.2b compliant ; Supports all DSC 1.2b mandatory encoding mechanisms ; MMAP, BP, MPP, and ICH ; Output buffering compatible with transport stream over video interfaces ; Configurable ...

4
VESA DSC (Display Stream Compression) 1.2b Video Decoder

VESA DSC 1.2b compliant ; Supports all DSC 1.2b mandatory encoding mechanisms ; MMAP, BP, MPP, and ICH ; Input buffering compatible with transport stream over video interfaces ; Configurable ...

5
ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder

The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to detect and report transient or permanent ...

6
VDC-M (VESA Display Compression-M) Encoder

The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliver visually lossless video compression. ...

7
VDC-M (VESA Display Compression-M) Decoder

The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. ...

8
VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs

Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC) ; Fully compliant with the DisplayPort 1.4a Standard ; Including the DSC slices per line ...

9
IPsec software toolkit

The Rambus IPsec Toolkit (previously QuickSec from Inside Secure) is client/server software for cloud and embedded security. It provides a complete software stack to build scalable IPsec VPN ...

10
VESA DisplayPort 2.0 FEC RX

The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 2.0 specification. Forward Error Correction ...

11
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC

The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphics cards, monitors, and laptops. Utilizing ...

12
Jitter Cleaner PLL Digital Loop Filter

The DPLL is a digital loop filter/controller designed to be used in conjunction with Silicon Creations Fractional-N PLLs. The resulting dual-loop PLL can attenuate jitter in extremely noisy ...

13
Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

Multiprotocol SerDes PMA supporting variety of interfaces.

1 Testimonial
Lyle Smith, Vice President of Product Development Engineering, Microsemi SoC BU

14
TSMC GF Intel Low Phase Noise, High-performance Digital LC PLL

Fractional-N LC based frequency synthesizer with digital loop filter for high performance clock generation applications. See our features list for more details.

15
Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more

Multiprotocol SerDes PMA supporting variety of interfaces.

16
Aeonic Generate Digital PLL for multi-instance, core logic clocking

The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality digital PLL that enables distributed clocking for per-core dynamic frequency scaling (DFS) and ...

17
Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium)

The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum computing. This IP core is engineered to provide ...

18
Post-Quantum Cryptography - nQrux® Secure Boot - Quantum-Secure Authenticated Boot (PQC)

nQrux® Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrity of binary images during the processor boot sequence. ...

19
On-chip Security Enclave - Digital IP delivered as RTL

Kudelski IoT Secure Hardware IP has been designed for chipset manufacturers seeking key protection in their system on chip (SoC/ASIC) solutions, robust cryptographic capabilities and services ...

20
Secure-IC's Securyzr™ Digital Sensor: Universal and Digital Fault Injection Attack Detector can be used across all processes

In cryptography, an attack can be performed by injecting one or several faults into a device thus disrupting the functional behavior of the device. Techniques commonly used to inject faults ...

21

Secure-IC's Securyzr™ Fully Digital Physically Unclonable Function (PUF) - PQC Ready

A Physically Unclonable Function (PUF) is a security mechanism that uses the inherent physical variations of a device to generate a unique, unclonable output. This output can be used as a ...

22

Secure-IC's Securyzr™ Tunable Public Key Cryptographic (RSA, ECDSA, SM2, Diffie-Hellman) accelerator - optional SCA protection

RSA is a public-key cryptosystem (the encryption key is public when the decryption key is private) widely used for secure data transmission. This IP provides comprehensive RSA encryption / ...

23

Unified Hardware IP for Post-Quantum Cryptography based on Kyber and Dilithium

PQSecure™-CRYSTALS from PQSecure Technologies, LLC. is a set of hardware IP cores designed for various target applications of digital signatures and key encapsulation based on Dilithium and ...

24

Turnkey UWB MAC and PHY platform IP, for FiRa 2.0, CCC Digital Key 3.0, and Radar

Ceva-Waves UWB is a low power ultra-wideband (UWB) MAC and PHY platform IP based on 802.15.4 HRP, the FiRa Consortium and the Car Connectivity Consortium Digital Key (CCC DK) requirements. ...

25

HDMI 2.1/DisplayPort 2.1 TX PHY in TSMC (N3E, N3P)

The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify ...

26

Securyzr Digital True Random Number Generator (TRNG) by Secure-IC, compliant with NIST SP800-90

Secure-IC offers both True Random Number Generator (TRNG) resilient to harmonic injection for statistically independent sets of bits generation and Deterministic Random Bit Generator (DRBG) ...

27

Complete Neural Processor for Edge AI

Akida first neuromorphic IP available on the market. Inspired by the biological function of neurons and engineered on a digital logic process, the Akida’s event-based spiking neural network ...

28

CRYSTALS-Dilithium - Post-Quantum Digital Signature IP Core

Post-quantum CRYSTALS-Dilithium Digital Signature IP Core from ResQuant supports key generation, signing and signature verification operations for II, III and IV level of security. Dilithium ...

29

DP/eDP1.4b RX PHY

Silicon Library's eDP/DP1.4b RX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is available in various fabs/nodes including ...

30

DP/eDP1.4b TX PHY

Silicon Library's eDP/DP1.4b TX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is available in various fabs/nodes including ...

31

On-chip Security Enclave - Digital IP delivered as RTL

Kudelski IoT Secure Hardware IP has been designed for chipset manufacturers seeking key protection in their system on chip (SoC/ASIC) solutions, robust cryptographic capabilities and services ...

32

400G : OTUC4 / 2xOTUC2 / 4xOTU4 Digital Wrapper

Alphawave offers a dynamically reconfigurable OTUC4 and 2xOTUC2 OTN (Callite-C4) digital wrapper IP core solution. The IP core is a perfect choice for carrying 400GE (IEEE 802.3bs) signal, ...

33

100G OTN Digital Core

The OTL4 core (Optical Transport Lane of OTU4) implements the OTL4 layer function of ITU-T G.709. The OTL4 interface can be used in OTU4 or OTUCn application. At the time of this page is ...

34

1.25G OTN Digital Wrapper

The OTU0/ODU0 Digital Wrapper IP Core offers 1.25G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation. Description In the source direction ...

35

2.5G OTN Digital Wrapper

The OTU1 Digital Wrapper IP Core offers 2.5G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation. Description In the source direction data ...

36

10G OTN Digital Wrapper

The OTU2/2e Digital Wrapper IP Core offers 10G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation. Description In the source direction ...

37

40G OTN Digital Wrapper

The OTU3 Digital Wrapper IP Core offers 40G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation. Description In the source direction data ...

38

100G OTN Digital Wrapper

The OTU4 Digital Wrapper IP Core offers 100G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation. In the source direction data is transferred ...

39

2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

The AresCORE 16G Die-to-Die (D2D) IP implements a wide-parallel and clock forwarded PHY interface for multichannel interconnections up to 16Gbps. The PHY IP is configurable to support the ...

40

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