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Vlsi design flow diagram IP Listing

I2C Master Controller w/FIFO (APB Bus)

I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)

I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)

I2C Master / Slave Controller w/FIFO (APB Bus)

I2C Master Controller w/FIFO (AHB & AHB-Lite Bus)

I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)

I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface

Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO

Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO

Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO

I2C Slave Controller - Low Power, Low Noise Config of User Registers

I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)

I2C Slave Controller - Low Power, Low Noise Config with APB Interface

I2C Slave Controller w/FIFO (AXI Bus)

I2C Slave Controller w/FIFO (APB Bus)

I2C Slave Controller w/FIFO (AHB Bus)

DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List

DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List

eSPI & SPI Master Controller w/FIFO

eSPI & SPI Slave Controller w/FIFO

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