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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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AES Encryption and Decryption
The CoreAES128 macro implements the advanced encryption standard (AES), which provides a means of securing data. AES utilizes the Rijndael algorithm, which is described in detail in the Federal Information Processing Standards Publication (FIPS PUB) 197.
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AES IP
- Secure-IC Securyzr™ Tunable Cryptography solutions with embedded side-channel protections: AES - SHA2 - SHA3 - PKC - RSA - ECC - Crystals Kyber - Crystals Dilithium - XMSS - LMS - SM2 - SM3 - SM4 - Whirlpool - CHACHA20 - Poly1305
- Secure-IC's Securyzr™ Tunable AES (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- 100G AES Encryption Core
- 10G/25G/40G/50G AES Encryption Core
- 400G AES Encryption Core