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AHB Subsystem
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus interfaces such as the BA22-DE, BA22-CE, ARM Cortex-M0/M0+/M1/M3/M4, and several RISC-V processors.
The AHB subsystem is available into versions: Base and Extended. The Base version (AHB-SBS-BASE) integrates a 32-bit multilayer AHB fabric with a Universal Serial Flash Controller, an SRAM controller and a set of APB peripherals. This version allows the host processor to boot directly from the flash, and execute code from the flash (eXecute In Place -XIP), or from an on-chip shadow SRAM. Furthermore, it provides access to the essential microcontroller peripherals, such as serial interfaces and timers.
The Extended version, the AHB-SBS-EXT, adds a multi-channel DMA, an SPI-to-AHB bridge, and an external memory controller, suitable for accessing off-chip parallel NOR-flash devices or SRAMs.
The AHB-SBS was designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. It is delivered in human-readable Verilog source code, along with comprehensive documentation for each module, example drivers, and. software exercising all the peripherals.
This subsystem can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.
The AHB subsystem is available into versions: Base and Extended. The Base version (AHB-SBS-BASE) integrates a 32-bit multilayer AHB fabric with a Universal Serial Flash Controller, an SRAM controller and a set of APB peripherals. This version allows the host processor to boot directly from the flash, and execute code from the flash (eXecute In Place -XIP), or from an on-chip shadow SRAM. Furthermore, it provides access to the essential microcontroller peripherals, such as serial interfaces and timers.
The Extended version, the AHB-SBS-EXT, adds a multi-channel DMA, an SPI-to-AHB bridge, and an external memory controller, suitable for accessing off-chip parallel NOR-flash devices or SRAMs.
The AHB-SBS was designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. It is delivered in human-readable Verilog source code, along with comprehensive documentation for each module, example drivers, and. software exercising all the peripherals.
This subsystem can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.
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Block Diagram of the AHB Subsystem IP Core
AHB IP
- SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
- AHB Octal SPI Controller with Execute in Place
- FlexNoC 5 Network-on-Chip (NoC)
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- CodaCache® Last Level Cache IP
- eMMC 5.1 Host Controller