MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
AI processing engine
The solution consists of:
* AON1010™ AI processing engine delivered in Verilog RTL. The RTL IP is suitable for logic synthesis targeting ASIC products as well as FPGA.
* AON1010™ AI software.
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Video Demo of the AI processing engine IP Core
AI IP
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