English
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
You are here:
AI processor (NPU) IP
・High-Performance:
Featuring a scalable architecture with over 40 TOPS computing power,
capable of handling a wide range of inference tasks.
・Multicore Parallel Processing:
A multicore design that can concurrently process multiple diverse models.
・Mixed Precision Computation:
Adopts a mixed precision computation approach to balance inference
performance and accuracy.
・Extensive Data Format Support:
Supports a broad range of data formats including INT4/8, FP4/FP8/FP16.
・Comprehensive Model Support:
ONNX support, enabling a diverse set of AI models.
・Edge Computing Optimization:
Optimized for edge computing with high PPA efficiency.
Featuring a scalable architecture with over 40 TOPS computing power,
capable of handling a wide range of inference tasks.
・Multicore Parallel Processing:
A multicore design that can concurrently process multiple diverse models.
・Mixed Precision Computation:
Adopts a mixed precision computation approach to balance inference
performance and accuracy.
・Extensive Data Format Support:
Supports a broad range of data formats including INT4/8, FP4/FP8/FP16.
・Comprehensive Model Support:
ONNX support, enabling a diverse set of AI models.
・Edge Computing Optimization:
Optimized for edge computing with high PPA efficiency.
View AI processor (NPU) IP full description to...
- see the entire AI processor (NPU) IP datasheet
- get in contact with AI processor (NPU) IP Supplier
Block Diagram of the AI processor (NPU) IP IP Core
AI IP
- RT-630 Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- NPU IP for Embedded AI
- RISC-V-based AI IP development for enhanced training and inference
- Tessent AI IC debug and optimization
- NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof