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AMBA AHB Direct Memory Acess (DMA) Controller
Features
- Multiple independent DMA channels with direct AHB bus interface.
- DMA transfers between AHB memory devices and I/O ports.
- Scatter-gather allows DMA to merge multiple data source to contiguous space.
- Supports both hardware initiated transfer and software initiated transfer.
- Supports burst transfer to maximize data bandwidth.
- Automatic address increment or decrement.
- Interrupt generation on transfer completion.
- Burst data access on the AHB interface and user I/O interface.
- Handles wait state insertion by any slave devices.
- Supports all slave device responses: OKAY, RETRY, SPLIT and ERROR.
- Master does not insert wait state on AHB bus thus maximize data bandwidth.
- No delay insertion on data transfer between user I/O interface and AHB bus.
- Separate user interface for DMA control register programming.
- User interface matches seamlessly with other Eureka Technology IP cores.
- Optimized for ASIC and PLD implementations.
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ARM AMBA AHB DMA Controller IP
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
- SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
- Display Controller - LCD / OLED Panels (AHB Bus)
- SPI Master / Slave Controller w/FIFO (APB Bus)