AMBA APB Bus Interface

CoreAPB is an AMBA bus interface that is used to connect subsystem cores to Microsemi's soft processors. The bus interface is easy to use and fully compatible with the APB protocol. The core is constructed for efficiency and allows easy connection of IP cores in systems built around the Cortex-M1, CoreMP7, Core8051s, or CoreABC processors.

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AMBA APB Bus Interface IP

SPI Master / Slave Controller w/FIFO (APB Bus)
eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
Configurable CAN Bus Controller IP with Flexible Data-Rate
SPI Master Controller w/FIFO (APB Bus)
AMBA APB 3.0 Bus Interface
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)

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