ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
Analog Front End: 1 channel of 12-bit 2 GSPS ADC IQ Pairs, 1 channel of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL
The ADC and DAC architecture is optimized to maximize performance while minimizing power and area consumption.
To maximize SNR, the AFE includes an ultra-low-jitter clock distribution network.
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Analog & Mixed Signal IP
- The tADC106-SW1-LR.01 is a mixed (analog and digital) Virtual Component (ViC) containing a three-channel ADC and additional functions offering an ideal mixed signal front end for low power and high quality audio applications.
- 7-bit, 64 GSPS ADC Ultra Low Power
- USB2.0 Host Transceiver PHY
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- Fibre-Channel Transceiver
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro