Scalable, On-Die Voltage Regulation for High Current Applications
Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
The AFE includes eight 12-bit, 2GSPS ADCs, four 12-bit 200MSPS ADCs, two TV monitors, multiple LDOs for ADC supplies, and a low jitter fractional-N PLL.
The ADC architecture is optimized to maximize performance while minimizing power and area consumption.
To maximize SNR, the AFE includes an ultra-low-jitter clock distribution network.
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Analog & Mixed Signal A2D Converter IP
- 7-bit, 64 GSPS ADC Ultra Low Power
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- Analog Front End: 8x 9-bit, 1 GSPS ADCs, PLL
- Analog Front End: 4 channels of 12-bit 2 GSPS ADC IQ Pairs, 4 channels of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL
- Analog Front End: 1 channel of 12-bit 2 GSPS ADC IQ Pairs, 1 channel of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL