APB I2C master and slave

The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB slave interface and so can be driven by software or via DMA.

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Block Diagram of the APB I2C master and slave

I2C IP

TSMC 6nm (6FF) 3.3V SMBUS (I2C) IO
TSMC 7nm (7FF) 3.3V SMBUS (I2C) IO
1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (22nm)
IO I2C 3.3V in GF (22nm)
1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
1.8V/3.3V I2C in GF (12nm)

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