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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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APB4 Multiplexer
The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. To enable a single APB4 Master to communicate with multiple APB4 Slaves (Peripherals) via a common bus, certain signals require multiplexing – the Roa Logic APB4 Multiplexer is a fully configurable & parameterized IP to provide this functionality.
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Block Diagram of the APB4 Multiplexer IP Core
