Area-efficient decision tree ensemble evaluation core based on serial evaluation of ensemble members

So_ip_edte_un_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consisting from decision tree with the previously defined structure directly in hardware. It uses a single module with area efficient sequential architecture to implement every DT from the ensemble using. This architecture has the lowest possible resource usage therefore enabling the very efficient implementation of DT ensembles, while still having a fairly fast classification speed.
So_ip_edte_un_s core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_edte_un_s design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_edte_un_s core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.

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