Register File with low power retention mode and 3 speed options
ASIP-1
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Block Diagram of the ASIP-1 IP Core

Programmable IP
- 512x8 Bits OTP (One-Time Programmable) IP, TSM- 12FFC 0.8V/1.8V Process
- Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel
- ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
- Programmable Low Power V-by-One SERDES - GLOBALFOUNDRIES 65 65G
- 4Kx8 Bits OTP (One-Time Programmable) IP, GLOBA-FOUNDR---® 22nm FDX 0.8V/1.8V Process
- Linear Li-Ion Battery Charger - Programmable charging current up to 1.1A Fast Charge in SilTerra 0.18um