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ASIP-2
The FFT/IFFT/DCT engine is an application specific instruction set processor (ASIP) optimized for the implementation of Fourier and cosine transforms, while also supporting general FIR equations.
The engine is divided into two main parts: a processing element, which deals directly with the data, and an embedded processor to control the signal flow by configuring the processing element. The system architecture is shown in the Fig.
The engine is divided into two main parts: a processing element, which deals directly with the data, and an embedded processor to control the signal flow by configuring the processing element. The system architecture is shown in the Fig.
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Block Diagram of the ASIP-2 IP Core
Reconfigurable IP
- Reconfigurable Parallel CRC Generator
- Low-power high-speed reconfigurable processor to accelerate AI everywhere.
- High Performance Media Processor
- PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
- High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS