AVC/H.264 Baseline encoder core

“H264EBH” is a highly integrated IP core specifically designed for highest quality video compression. With H.264EBH, encoding high definition content requires 0 processor resources. Further, advanced system prototyping support and flexible SoC integration are key features in our design mentality. H.264 EBH is in full compliance to ISO/IEC 14496-10 (ITU-T H.264 or MPEG-4 part10/AVC) video coding standard. It is designed to offer the maximum level of performance and compression quality at the lowest possible bit-rate with minimal power and silicon requirements. Supported resolutions range from QCIF(176x120) up to 2048x2048 at 30 fps or more. Multi-core instantiation is also possible in order to offer multichannel encoding and maximum performance up to real time full HD. Our core accepts standard digital video input and requires minimal host intervention, constrained to typical register access, in order to produce a fully formed NAL video stream. It can be interfaced to any host through a generic system interface.

Our core’s architecture allows flexible and highly competitive combination of encoding features in order to offer maximum video quality solutions tailored for different FPGA devices or SoC platforms. H.264 EBH supports HDTV video compression (720p) even when implemented in the modest VLSI (0.18um) technology. For FPGA implementations, full D1 resolution at 30 frames per second with a single core is supported.

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