English
10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
You are here:
AXI CAN
The LogiCORE™ IP Controller Area Network (CAN) product specification defines the architecture and features of the Xilinx CAN controller core. This document also defines the addressing and functionality of the various registers in the design, in addition to describing the user interface.
View AXI CAN full description to...
- see the entire AXI CAN datasheet
- get in contact with AXI CAN Supplier
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC