English
You are here:
AXI Datamover
Included at no additional charge with ISE software
Xilinx provides the AXI Datamover core which provides high throughput transfer of data from AXI4 memory mapped domain to AXI4-Stream domain and back.
The AXI Datamover is a key Interconnect Infrastructure IP which enables high throughput transfer of data between AXI4 memory mapped domain to AXI4-Stream domain. The AXI Datamover provides MM2S and S2MM AXI4-Stream channel which operate independently in a full duplex like method. The AXI Datamover is a key building block for the AXI DMA core and enables 4 kbyte address boundary protection, automatic burst partitioning, as well as providing the ability to queue multiple transfer requests using nearly the full bandwidth capabilities of the AXI4-Stream protocol. Furthermore, the AXI Datamover provides byte-level data realignment allowing memory reads and writes to any byte offset location.
Xilinx provides the AXI Datamover core which provides high throughput transfer of data from AXI4 memory mapped domain to AXI4-Stream domain and back.
The AXI Datamover is a key Interconnect Infrastructure IP which enables high throughput transfer of data between AXI4 memory mapped domain to AXI4-Stream domain. The AXI Datamover provides MM2S and S2MM AXI4-Stream channel which operate independently in a full duplex like method. The AXI Datamover is a key building block for the AXI DMA core and enables 4 kbyte address boundary protection, automatic burst partitioning, as well as providing the ability to queue multiple transfer requests using nearly the full bandwidth capabilities of the AXI4-Stream protocol. Furthermore, the AXI Datamover provides byte-level data realignment allowing memory reads and writes to any byte offset location.
View AXI Datamover full description to...
- see the entire AXI Datamover datasheet
- get in contact with AXI Datamover Supplier
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC