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AXI SmartConnect
The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.
The AXI SmartConnect is a Hierarchical IP block that is added to a Vivado® IP Integrator block design in the Vivado Design Suite.
AXI SmartConnect is a drop-in replacement for the AXI Interconnect v2 core. AXI SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention.
The AXI SmartConnect is a Hierarchical IP block that is added to a Vivado® IP Integrator block design in the Vivado Design Suite.
AXI SmartConnect is a drop-in replacement for the AXI Interconnect v2 core. AXI SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC