English
NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
You are here:
AXI4-Stream to Video Out
Included at no additional charge with ISE software. Xilinx AXI4-Stream to Video Out IP core enables video designers to quickly and easily connect video processing blocks that use AXI4-Stream to external video sinks.
The AXI-4 Stream to Video Out LogiCORE™ IP core converts AXI4-Stream interface signals to a standard parallel video output interface with timing signals. The AXI4-Stream interface accepts signals that are compliant to the AXI4-Stream Video Protocol as defined in the AXI Reference Guide (UG761), and as is implemented on most Xilinx Video IP cores. The output interface is suitable for use with many external video sinks and contains standard video timing signals including Vsync, Hsync, Vblank, Hblank, DE and pixel clock. This enables video designers to quickly and easily connect video processing blocks with an AXI4-Stream interface to an external video sink such as a DVI PHY. This core works in conjunction with the Xilinx Video Timing Controller (VTC) core to generate the video format timing signals. Source code is provided with the core to allow customers to adapt the core to work with unique video signals that may not already be included in the core.
The AXI-4 Stream to Video Out LogiCORE™ IP core converts AXI4-Stream interface signals to a standard parallel video output interface with timing signals. The AXI4-Stream interface accepts signals that are compliant to the AXI4-Stream Video Protocol as defined in the AXI Reference Guide (UG761), and as is implemented on most Xilinx Video IP cores. The output interface is suitable for use with many external video sinks and contains standard video timing signals including Vsync, Hsync, Vblank, Hblank, DE and pixel clock. This enables video designers to quickly and easily connect video processing blocks with an AXI4-Stream interface to an external video sink such as a DVI PHY. This core works in conjunction with the Xilinx Video Timing Controller (VTC) core to generate the video format timing signals. Source code is provided with the core to allow customers to adapt the core to work with unique video signals that may not already be included in the core.
View AXI4-Stream to Video Out full description to...
- see the entire AXI4-Stream to Video Out datasheet
- get in contact with AXI4-Stream to Video Out Supplier
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC