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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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Cap-less 25mA Low Noise LDO, Fujitsu 90nm
The AR25F01 is a mass-production proven cap-less LDO IP. It is capable of outputting 1.2V voltage with maximum power of 20mA and low drop out voltage of less than 200mV. The IP is fabricated in Fujitsu 90nm process and can be ported to other process nodes.
Supported by innovative and dedicated analog mixed-signal engineering teams in Silicon Valley and Asia, we are specialized in high performance low power audio CODECs, pipelined A/D converters, current-steering D/A converters, PLL, DLL clocking IPs, and high speed IO interface IPs. Please contact us for more information.
Supported by innovative and dedicated analog mixed-signal engineering teams in Silicon Valley and Asia, we are specialized in high performance low power audio CODECs, pipelined A/D converters, current-steering D/A converters, PLL, DLL clocking IPs, and high speed IO interface IPs. Please contact us for more information.
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LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL