1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
Cap-less 25mA Low Noise LDO, Fujitsu 90nm
Supported by innovative and dedicated analog mixed-signal engineering teams in Silicon Valley and Asia, we are specialized in high performance low power audio CODECs, pipelined A/D converters, current-steering D/A converters, PLL, DLL clocking IPs, and high speed IO interface IPs. Please contact us for more information.
View Cap-less 25mA Low Noise LDO, Fujitsu 90nm full description to...
- see the entire Cap-less 25mA Low Noise LDO, Fujitsu 90nm datasheet
- get in contact with Cap-less 25mA Low Noise LDO, Fujitsu 90nm Supplier
LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL