Charter 0.13um 1.2v APLL

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting different values of DM(5:0) and DN(6:0) according to different REFIN, CLK will be locked at the multiples of input frequency.

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PLL phase locked loop IP

Phase Locked Loop (PLL) Frequency Synthesizer Core
Phase Locked Loop (PLL) Module
Phase Locked Loop (PLL) Macro
200 MHz—800 Mhz Phase Locked Loop IP Block
5GHz to 13.5GHz Phase Locked Loop IP Block
2000 to 2800 MHz Phase Locked Loop

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