English
1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (22nm)
You are here:
ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-5 GTP
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex-5 GTP is a customizable core that can be used to evaluate and monitor the health of Virtex-5 GTP Transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the MGTs. Communication logic is also included, to allow the design to be runtime accessible through JTAG. The IBERT core is a self-contained design, and when it is generated, will run through the entire implementation flow, including bitstream generation.
View ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-5 GTP full description to...
- see the entire ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-5 GTP datasheet
- get in contact with ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-5 GTP Supplier
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC