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ChipScope Pro IBERT for 7 Series GTH
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Kintex™-7 FPGA GTX transceivers is a customizable core that can be used to evaluate and monitor the health of Kintex-7 FPGA GTX transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and dynamic reconfiguration port (DRP) attributes of the GTX transceivers.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC