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ChipScope Pro IBERT for 7 Series GTZ
The customizable LogiCORE™ IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTZ transceivers is designed for evaluating and monitoring the GTZ transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTZ transceivers. Communication logic is also included to allow the design to be run-time accessible through JTAG. This core can be used as a self-contained or open design, based on customer configuration, and as described in this document.
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Interface and Interconnect IP
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- Serial Peripheral Interconnect Master & Slave Interface Controller
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- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC