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LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
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ChipScope Pro IBERT for Spartan-6 GTP Transceivers
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for the Spartan®-6 GTP transceiver is a customizable core that can be used to evaluate and monitor the health of the Spartan-6 GTP transceivers. The design includes pattern generators and checkers implemented in Field Programmable Gate Array (FPGA) logic, as well as access to the ports and dynamic reconfiguration port (Dynamic Reconfiguration Port) DPR attributes of the serial transceivers. Communication logic is also included and allows the design to be run-time accessible through Joint Test Action Group (JTAG). The IBERT core is a self-contained design, and when generated, runs through the entire implementation flow, including bit stream generation.
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