Clock Delay Monitor IP

Synopsys’ Clock and Delay Monitor (CDM) is a small IP capable of performing on-chip measurements, monitoring, and safety operations. It can be embedded into silicon with minimal area overhead, does not need any precise high speed reference clock, and provides accurate on-chip measurement and monitoring of memory and clock characteristics, such as clock duty cycle, frequency, memory data output time, delay line characteristics, etc. It is provided with an IEEE 1500/1687 interface to facilitate its connection to a test fabric. Generally, Synopsys’ functional monitors are enabled with EDA and software automation for ease of use.

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