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Common Flash Interface
CoreCFI provides an external interface to the embedded Flash memory blocks within the Fusion devices with which a user will be able to communicate (i.e. read, write, and erase) to the embedded Flash memory. This IP block provides a functional subset of the Common Flash Interface with a design emphasis to minimize design size.
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Block Diagram of the Common Flash Interface IP Core
Common Flash Interface IP
- Compact Flash host interface controller with APB interface.
- NAND Flash controller supporting MLC Flash with multi-bit correction BCH ECC code
- MIPI M-PHY Gear 5 for TSMC N3E
- MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
- On-chip Nonvolatile AHB Memory Controller
- Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP