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Configurable UART with FIFO, hardware and software flow control
The D16752 is a universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs and automatic hardware/software flow control. It offers enhanced features, like transmission control register (TCR), that stores received FIFO threshold level, to start/stop transmission during hardware and sofware flow control. With the FIFO RDY register, the software gets a status of TXRDY/RXRDY for all UART ports in one access. Onboard status registers provide the user with error indications and an operational status modem interface control. System interrupts may be tailored to meet your requirements. An internal loopback capability allows onboard diagnostics. The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7 or 8 bits. The UART has a 64-byte receive FIFO and a transmit FIFO, which can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate, based upon a programmable divisor and its input clock. It can transmit even, odd or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow and parity errors. On the other hand, the transmitter can detect a FIFO underflow. The UART also contains a software interface for modem control operations and has a software flow control, combined with hardware flow control capabilities. The D16752 is software compatible with the TL16C752 . It provides few enhanced features, which are provided through a special enhanced feature register. The UART will perform a serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the D16752 can be read by the CPU at any time during functional operation. Our efficient core can be placed in an alternate mode (FIFO mode), relieving the processor of excessive software overhead, which is run by buffering received/transmitted characters. Both, the receiver and the transmitter FIFOs, can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers. The D16752 has a selectable hardware flow control and a software flow control.
The hardware flow control significantly reduces software overhead and increases system efficiency, by automatically controlled serial data flow using the RTS output and CTS input signals.
Software flow control automatically monitors data flow, by using programmable Xon/Xoff characters.The UART includes a programmable baud rate generator, that can divide the timing reference clock input by a divisor between 1 and (216-1).
The separate BAUD CLK line allow to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.
D16752 includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. Our efficient Core is a technology independent design, that can be implemented in a variety of process technologies.
The configuration capability allows you to enable or disable during the Synthesis process the Modem Control Logic and the FIFO's Control Logic and change the FIFO size. So, in applications with area limitation and where the UART works only in a 16450 mode, disabling the Modem Control and FIFO's allow to save about 50% of logic resources.
The Core is perfect for applications, where the UART core and a microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Nevertheless, our solution is designed for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks the D16752, the CPU interface core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.
The D16752 UART Core can operate as dual channel, as well as single channel UART.
The hardware flow control significantly reduces software overhead and increases system efficiency, by automatically controlled serial data flow using the RTS output and CTS input signals.
Software flow control automatically monitors data flow, by using programmable Xon/Xoff characters.The UART includes a programmable baud rate generator, that can divide the timing reference clock input by a divisor between 1 and (216-1).
The separate BAUD CLK line allow to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.
D16752 includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. Our efficient Core is a technology independent design, that can be implemented in a variety of process technologies.
The configuration capability allows you to enable or disable during the Synthesis process the Modem Control Logic and the FIFO's Control Logic and change the FIFO size. So, in applications with area limitation and where the UART works only in a 16450 mode, disabling the Modem Control and FIFO's allow to save about 50% of logic resources.
The Core is perfect for applications, where the UART core and a microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Nevertheless, our solution is designed for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks the D16752, the CPU interface core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.
The D16752 UART Core can operate as dual channel, as well as single channel UART.
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