55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
CORDIC
The Lattice CORDIC IP is configurable and several functions can be implemented in the IP core: Rotation, Translation, Sin and Cos, Arctan. Two architecture configurations are available for the arithmetic unit: Parallel, with single cycle data throughput, and Word-serial, with multiple cycles throughput. The input data, output data widths and iterative number are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for rounding.
View CORDIC full description to...
- see the entire CORDIC datasheet
- get in contact with CORDIC Supplier
Block Diagram of the CORDIC IP Core
FPGA IP
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Ethernet TSN Switch IP Core - Efficient and Massively Customizable
- CXL 2.0 Agilex FPGA Acclerator Card
- PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes