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D2D CONTROLLER
The InPsytech high-speed D2D Controller IP, optimized for power and latency enables die-to-die or chiplet-to-chiplet connectivity in applications like network, HPC, AI and server SoCs. The controller interoperates seamlessly with InPsytech D2D PHY to deliver a complete between-die (chiplet) solution vias the standard AXI ports.
The D2D controller IP implements an error detection and correction mechanism such as Cycle Redundancy Check (CRC) to reduce Bit Error Rate (BER). Optimized to operate with the InPsytech D2D PHY, the D2D controller can directly operate with the PHY to monitor the data transmission with per-bit data eye monitors as well as the voltage and temperature adaptive receiver to enable simultaneously transmit and receive with continuous data transmission without error and interruption.
The D2D Controller and the D2D PHY (TSMC N5/N4P) are silicon proven in both INFO and CoWoSTM package technology. For further information about the Controller and the PHY, please contact representative at sales@inpsytech.com.
The D2D controller IP implements an error detection and correction mechanism such as Cycle Redundancy Check (CRC) to reduce Bit Error Rate (BER). Optimized to operate with the InPsytech D2D PHY, the D2D controller can directly operate with the PHY to monitor the data transmission with per-bit data eye monitors as well as the voltage and temperature adaptive receiver to enable simultaneously transmit and receive with continuous data transmission without error and interruption.
The D2D Controller and the D2D PHY (TSMC N5/N4P) are silicon proven in both INFO and CoWoSTM package technology. For further information about the Controller and the PHY, please contact representative at sales@inpsytech.com.
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Block Diagram of the D2D CONTROLLER IP Core
