MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/150mA, with soft-start, UMC 0.13um LL/FSG process
View DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/150mA, with soft-start, UMC 0.13um LL/FSG process full description to...
- see the entire DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/150mA, with soft-start, UMC 0.13um LL/FSG process datasheet
- get in contact with DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/150mA, with soft-start, UMC 0.13um LL/FSG process Supplier
Power IP IP
- Multi-Protocol Crypto Packet Engine, Low Power, Bus Attached
- Low-Latency SerDes PMA
- Power Deliver Network Monitoring and Droop Detection
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP
- Complete USB Type-C Power Delivery PHY, RTL, and Software