Fractional-N Integer LC DESKEW PLLs in FDSOI FDX (GF22FDX SS28FDS ST28FD-SOI 22FDX 28FDS)
DDR, Digital Configurable Delay line module
Configuration resolution is 4Bits.
The DDR module set , position and align the strobe Tap at configurable fractional input clock cycle after the clock edge.
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