NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
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PLL/DLL IP
- Programmable DLL, fully digital PLL - TSMC 28nm 28HP (CLN28HP)
- Programmable DLL, fully digital PLL - TSMC 40nm 40G (CLN40G)
- Programmable DLL, fully digital PLL - TSMC 40nm 40LP (CLN40lp)
- Fully Digital Glitch Free PLL TSMC HPC+28nm - 200-2000 MHz
- High Performance Fractional-N RF Frequency Synthesizer PLL in UMC 40LP
- Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX